Hasso-Plattner-Institut für Softwaresystemtechnik
VLSI - Design and Verification

Contact

Prof. Dr. Christoph Meinel

Hasso-Plattner-Institut
an der Universität Potsdam

Tel: +49 0331/5509-222
Fax: +49 0331/5509-325
Mobil: +49 176 10010727
meinel"at"hpi.uni-potsdam.de

Books

VLSI - Design and Verification

Research Topic: Accelerating the Variable Reordering Process

The only way to decrease the size of BDDs is by finding better variable orders. The most powerful method is dynamic reordering during the construction of the BDD. Unfortunately common reordering strategies are sometimes too time consuming.

We have introduced different techniques for accelerating the process of variable reordering. These techniques utitlize either structural or semantical information from the given BDDs. These techniques have been applied to different tasks like combinatorical verification, reachability analysis and symbolic model checking.

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Activities:

  • OHO :  OBDD Heuristics Online